====== Action Items.  PM#3 ======


^AI ^Title ^  ^Responsible ^  ^  ^Status ^Comments |
|7588 |Decide how to   conduct the N-DPU BB and N-FEE BB I/F tests |Decide how to   conduct the N-DPU BB and N-FEE BB I/F tests    \\   \\ An idea should be documented for the PDCR data package. |Juan-Carlos   Suarez |IAA |07/05/2015 |Open |En el pm2 fue   abierto. En desarrollo. Hay que ver los test que se quieren/pueden hacer. |
|10856 |RID   Action Item ADS-91 |RID   Title: FPGA utilisation analysis    \\ RID Number: Industry ADS-91    \\ Originator Reference:     \\ Datapack Document: PLATO-IAA-PL-DD-001 |Juan-Carlos   Suarez |IAA |01/10/2015 |Open |En el pm3. En   SRR se indicará |
|10850 |RID   Action Item ADS-30 |RID   Title: FPGA blocks    \\ RID Number: Industry ADS-30    \\ Originator Reference:     \\ Datapack Document: PLATO-LESIA-PL-DD-001 |Juan-Carlos   Suarez |IAA |01/10/2015 |Open |En el pm3. En   SRR se indicará |
|10845 |RID   Action Item TAS-8 |RID   Title: Cross strapping of MEUs and cameras    \\ RID Number: Industry TAS-8    \\ Originator Reference: AA-5    \\ Datapack Document: PLATO-DLR-PL-RS-001 |Peter   Gisbert |DLR |08/05/2015 |Open |Esto es interno del SVM. Ver si   se ha contestado en PM3 |
|8968 |Verify   the feasibility of 200Mbit on the Spacewire I/F on the N-FEE to N-DPU |Constrains   are on the N-FEE and not the N-DPU side. Thus it needs to be analysed if it   is possible to work with 200Mbit on space wire. |Tom   Kennedy |MSSL |16/07/2015 |Open |OJOOOOOOOOO |


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